linux-libre-lts{,-knock}: fix patches for C.H.I.P

10 files changed, 21 insertions, 575 deletions

diff --git a/libre/linux-libre-lts/0001-ARM-sunxi-Add-R8-support.patch b/libre/linux-libre-lts/0001-ARM-sunxi-Add-R8-support.patch
index 4d8194026..957a7a2ff 100644
--- a/libre/linux-libre-lts/0001-ARM-sunxi-Add-R8-support.patch
+++ b/libre/linux-libre-lts/0001-ARM-sunxi-Add-R8-support.patch
@@ -1,7 +1,7 @@
 From bef6229f36c1c2ddae186f4e328c2359c1dad18d Mon Sep 17 00:00:00 2001
 From: Maxime Ripard <maxime.ripard@free-electrons.com>
 Date: Tue, 9 Jun 2015 19:38:04 +0200
-Subject: [PATCH 1/9] ARM: sunxi: Add R8 support
+Subject: [PATCH 1/5] ARM: sunxi: Add R8 support
 
 The R8 is a new Allwinner SoC based on the A13. While both are very
 similar, there's still a few differences. Introduce a new compatible to
diff --git a/libre/linux-libre-lts/0002-ARM-sun5i-Add-CHIP-DTS.patch b/libre/linux-libre-lts/0002-ARM-sun5i-Add-CHIP-DTS.patch
index 296182aa7..7db5ff94f 100644
--- a/libre/linux-libre-lts/0002-ARM-sun5i-Add-CHIP-DTS.patch
+++ b/libre/linux-libre-lts/0002-ARM-sun5i-Add-CHIP-DTS.patch
@@ -1,7 +1,7 @@
 From 465a225fb2afb3ebf1becbe76d46b084d46f30a5 Mon Sep 17 00:00:00 2001
 From: Maxime Ripard <maxime.ripard@free-electrons.com>
 Date: Tue, 9 Jun 2015 19:38:43 +0200
-Subject: [PATCH 2/9] ARM: sun5i: Add C.H.I.P DTS
+Subject: [PATCH 2/5] ARM: sun5i: Add C.H.I.P DTS
 
 The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
 RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
diff --git a/libre/linux-libre-lts/0004-ARM-sun5i-Add-R8-DTSI.patch b/libre/linux-libre-lts/0003-ARM-sun5i-Add-R8-DTSI.patch
index 5c97fd48c..e8b1099c1 100644
--- a/libre/linux-libre-lts/0004-ARM-sun5i-Add-R8-DTSI.patch
+++ b/libre/linux-libre-lts/0003-ARM-sun5i-Add-R8-DTSI.patch
@@ -1,7 +1,7 @@
 From 49e4f3c3271e7eff2800596ba168c932d7d702b8 Mon Sep 17 00:00:00 2001
 From: Maxime Ripard <maxime.ripard@free-electrons.com>
 Date: Fri, 18 Sep 2015 09:09:34 +0200
-Subject: [PATCH 4/9] ARM: sun5i: Add R8 DTSI
+Subject: [PATCH 3/5] ARM: sun5i: Add R8 DTSI
 
 The R8 is very close to the A13, but it still has a few differences,
 notably a composite output, which the A13 lacks.
@@ -14,16 +14,16 @@ Reviewed-by: Hans de Goede <hdegoede@redhat.com>
 Reviewed-by: André Silva <emulatorman@parabola.nu>
 Reviewed-by: Márcio Silva <coadde@parabola.nu>
 ---
- arch/arm/boot/dts/sun5i-r8.dtsi | 750 +++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 750 insertions(+)
+ arch/arm/boot/dts/sun5i-r8.dtsi | 719 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 719 insertions(+)
  create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi
 
 diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
 new file mode 100644
-index 0000000..75a9960
+index 0000000..5d76b20
 --- /dev/null
 +++ b/arch/arm/boot/dts/sun5i-r8.dtsi
-@@ -0,0 +1,750 @@
+@@ -0,0 +1,719 @@
 +/*
 + * Copyright 2015 Free Electrons
 + * Copyright 2015 NextThing Co
@@ -73,7 +73,6 @@ index 0000000..75a9960
 +
 +#include <dt-bindings/thermal/thermal.h>
 +
-+#include <dt-bindings/clock/sun4i-a10-pll2.h>
 +#include <dt-bindings/dma/sun4i-a10.h>
 +#include <dt-bindings/pinctrl/sun4i-a10.h>
 +
@@ -204,15 +203,6 @@ index 0000000..75a9960
 +			clock-output-names = "pll1";
 +		};
 +
-+		pll2: clk@01c20008 {
-+			#clock-cells = <1>;
-+			compatible = "allwinner,sun5i-a13-pll2-clk";
-+			reg = <0x01c20008 0x8>;
-+			clocks = <&osc24M>;
-+			clock-output-names = "pll2-1x", "pll2-2x",
-+					     "pll2-4x", "pll2-8x";
-+		};
-+
 +		pll4: clk@01c20018 {
 +			#clock-cells = <0>;
 +			compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -419,14 +409,6 @@ index 0000000..75a9960
 +			clock-output-names = "usb_ohci0", "usb_phy";
 +		};
 +
-+		codec_clk: clk@01c20140 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-a10-codec-clk";
-+			reg = <0x01c20140 0x4>;
-+			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
-+			clock-output-names = "codec";
-+		};
-+
 +		mbus_clk: clk@01c2015c {
 +			#clock-cells = <0>;
 +			compatible = "allwinner,sun5i-a13-mbus-clk";
@@ -691,19 +673,6 @@ index 0000000..75a9960
 +			status = "disabled";
 +		};
 +
-+		codec: codec@01c22c00 {
-+			#sound-dai-cells = <0>;
-+			compatible = "allwinner,sun4i-a10-codec";
-+			reg = <0x01c22c00 0x40>;
-+			interrupts = <30>;
-+			clocks = <&apb0_gates 0>, <&codec_clk>;
-+			clock-names = "apb", "codec";
-+			dmas = <&dma SUN4I_DMA_NORMAL 19>,
-+			       <&dma SUN4I_DMA_NORMAL 19>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
 +		sid: eeprom@01c23800 {
 +			compatible = "allwinner,sun4i-a10-sid";
 +			reg = <0x01c23800 0x10>;
diff --git a/libre/linux-libre-lts/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch b/libre/linux-libre-lts/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch
deleted file mode 100644
index e9b2c566c..000000000
--- a/libre/linux-libre-lts/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From e54693ed82ae0fee934a21328536751afd293c80 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 28 Jul 2015 10:37:01 +0200
-Subject: [PATCH 3/9] ARM: sun5i: chip: Enable the audio codec
-
-The CHIP v0.2 has a composite output on a mini-jack connector, the audio
-part being provided by the on-SoC codec. Enable it.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
-index abf3ccb..530ab28 100644
---- a/arch/arm/boot/dts/sun5i-r8-chip.dts
-+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
-@@ -66,6 +66,10 @@
- 	};
- };
- 
-+&codec {
-+	status = "okay";
-+};
-+
- &ehci0 {
- 	status = "okay";
- };
--- 
-cgit v0.12
-
diff --git a/libre/linux-libre-lts/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch b/libre/linux-libre-lts/0004-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch
index 82484923a..b9333b202 100644
--- a/libre/linux-libre-lts/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch
+++ b/libre/linux-libre-lts/0004-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch
@@ -1,7 +1,7 @@
 From 5b3abbee42562a7bcdc6b589a3d8f9b5752550ed Mon Sep 17 00:00:00 2001
 From: Hans de Goede <hdegoede@redhat.com>
 Date: Tue, 22 Sep 2015 15:36:00 +0200
-Subject: [PATCH 7/9] ARM: dts: axp209: Add usb_power_supply child node to the ax209 node
+Subject: [PATCH 4/5] ARM: dts: axp209: Add usb_power_supply child node to the ax209 node
 
 Add a node representing the usb power supply part of the axp209 pmic, note
 that the usb power supply and the (to be added later) ac power supply will
diff --git a/libre/linux-libre-lts/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch b/libre/linux-libre-lts/0005-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch
index fc7418ab2..3128e7cd5 100644
--- a/libre/linux-libre-lts/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch
+++ b/libre/linux-libre-lts/0005-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch
@@ -1,7 +1,7 @@
 From db30fce1eea58e50ae8b2722704b4f529c394dba Mon Sep 17 00:00:00 2001
 From: Maxime Ripard <maxime.ripard@free-electrons.com>
 Date: Wed, 25 Nov 2015 16:39:04 +0100
-Subject: [PATCH 8/9] ARM: sun5i: chip: Add CPU regulator for cpufreq
+Subject: [PATCH 5/5] ARM: sun5i: chip: Add CPU regulator for cpufreq
 
 The current DT doesn't have a phandle to the CPU regulator in the CPU node,
 which disables the CPU voltage scaling entirely.
diff --git a/libre/linux-libre-lts/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch b/libre/linux-libre-lts/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch
deleted file mode 100644
index e1c185e0e..000000000
--- a/libre/linux-libre-lts/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch
+++ /dev/null
@@ -1,299 +0,0 @@
-From 460d0d444822e9032a2573fc051b45c68b89a97a Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 18 Jul 2014 15:48:35 -0300
-Subject: [PATCH 5/9] clk: sunxi: Add a driver for the PLL2
-
-The PLL2 on the A10 and later SoCs is the clock used for all the audio
-related operations.
-
-This clock has a somewhat complex output tree, with three outputs (2X, 4X
-and 8X) with a fixed divider from the base clock, and an output (1X) with a
-post divider.
-
-However, we can simplify things since the 1X divider can be fixed, and we
-end up by having a base clock not exposed to any device (or at least
-directly, since the 4X output doesn't have any divider), and 4 fixed
-divider clocks that will be exposed.
-
-This clock seems to have been introduced, at least in this form, in the
-revision B of the A10, but we don't have any information on the clock used
-on the revision A.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Reviewed-by: Chen-Yu Tsai <wens@csie.org>
----
- drivers/clk/sunxi/Makefile                 |   1 +
- drivers/clk/sunxi/clk-a10-pll2.c           | 188 +++++++++++++++++++++++++++++
- include/dt-bindings/clock/sun4i-a10-pll2.h |  53 ++++++++
- 3 files changed, 242 insertions(+)
- create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c
- create mode 100644 include/dt-bindings/clock/sun4i-a10-pll2.h
-
-diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
-index f5a35b8..c658a18 100644
---- a/drivers/clk/sunxi/Makefile
-+++ b/drivers/clk/sunxi/Makefile
-@@ -4,6 +4,7 @@
- 
- obj-y += clk-sunxi.o clk-factors.o
- obj-y += clk-a10-hosc.o
-+obj-y += clk-a10-pll2.o
- obj-y += clk-a20-gmac.o
- obj-y += clk-mod0.o
- obj-y += clk-simple-gates.o
-diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
-new file mode 100644
-index 0000000..a57742a
---- /dev/null
-+++ b/drivers/clk/sunxi/clk-a10-pll2.c
-@@ -0,0 +1,188 @@
-+/*
-+ * Copyright 2013 Emilio López
-+ * Emilio López <emilio@elopez.com.ar>
-+ *
-+ * Copyright 2015 Maxime Ripard
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/clock/sun4i-a10-pll2.h>
-+
-+#define SUN4I_PLL2_ENABLE		31
-+
-+#define SUN4I_PLL2_PRE_DIV_SHIFT	0
-+#define SUN4I_PLL2_PRE_DIV_WIDTH	5
-+#define SUN4I_PLL2_PRE_DIV_MASK		GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
-+
-+#define SUN4I_PLL2_N_SHIFT		8
-+#define SUN4I_PLL2_N_WIDTH		7
-+#define SUN4I_PLL2_N_MASK		GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
-+
-+#define SUN4I_PLL2_POST_DIV_SHIFT	26
-+#define SUN4I_PLL2_POST_DIV_WIDTH	4
-+#define SUN4I_PLL2_POST_DIV_MASK	GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
-+
-+#define SUN4I_PLL2_POST_DIV_VALUE	4
-+
-+#define SUN4I_PLL2_OUTPUTS		4
-+
-+static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
-+
-+static void __init sun4i_pll2_setup(struct device_node *node)
-+{
-+	const char *clk_name = node->name, *parent;
-+	struct clk **clks, *base_clk, *prediv_clk;
-+	struct clk_onecell_data *clk_data;
-+	struct clk_multiplier *mult;
-+	struct clk_gate *gate;
-+	void __iomem *reg;
-+	u32 val;
-+
-+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
-+	if (IS_ERR(reg))
-+		return;
-+
-+	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
-+	if (!clk_data)
-+		goto err_unmap;
-+
-+	clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
-+	if (!clks)
-+		goto err_free_data;
-+
-+	parent = of_clk_get_parent_name(node, 0);
-+	prediv_clk = clk_register_divider(NULL, "pll2-prediv",
-+					  parent, 0, reg,
-+					  SUN4I_PLL2_PRE_DIV_SHIFT,
-+					  SUN4I_PLL2_PRE_DIV_WIDTH,
-+					  CLK_DIVIDER_ONE_BASED |
-+					  CLK_DIVIDER_ALLOW_ZERO,
-+					  &sun4i_a10_pll2_lock);
-+	if (!prediv_clk) {
-+		pr_err("Couldn't register the prediv clock\n");
-+		goto err_free_array;
-+	}
-+
-+	/* Setup the gate part of the PLL2 */
-+	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-+	if (!gate)
-+		goto err_unregister_prediv;
-+
-+	gate->reg = reg;
-+	gate->bit_idx = SUN4I_PLL2_ENABLE;
-+	gate->lock = &sun4i_a10_pll2_lock;
-+
-+	/* Setup the multiplier part of the PLL2 */
-+	mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
-+	if (!mult)
-+		goto err_free_gate;
-+
-+	mult->reg = reg;
-+	mult->shift = SUN4I_PLL2_N_SHIFT;
-+	mult->width = 7;
-+	mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
-+			CLK_MULTIPLIER_ROUND_CLOSEST;
-+	mult->lock = &sun4i_a10_pll2_lock;
-+
-+	parent = __clk_get_name(prediv_clk);
-+	base_clk = clk_register_composite(NULL, "pll2-base",
-+					  &parent, 1,
-+					  NULL, NULL,
-+					  &mult->hw, &clk_multiplier_ops,
-+					  &gate->hw, &clk_gate_ops,
-+					  CLK_SET_RATE_PARENT);
-+	if (!base_clk) {
-+		pr_err("Couldn't register the base multiplier clock\n");
-+		goto err_free_multiplier;
-+	}
-+
-+	parent = __clk_get_name(base_clk);
-+
-+	/*
-+	 * PLL2-1x
-+	 *
-+	 * This is supposed to have a post divider, but we won't need
-+	 * to use it, we just need to initialise it to 4, and use a
-+	 * fixed divider.
-+	 */
-+	val = readl(reg);
-+	val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
-+	val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT;
-+	writel(val, reg);
-+
-+	of_property_read_string_index(node, "clock-output-names",
-+				      SUN4I_A10_PLL2_1X, &clk_name);
-+	clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
-+							    parent,
-+							    CLK_SET_RATE_PARENT,
-+							    1,
-+							    SUN4I_PLL2_POST_DIV_VALUE);
-+	WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
-+
-+	/*
-+	 * PLL2-2x
-+	 *
-+	 * This clock doesn't use the post divider, and really is just
-+	 * a fixed divider from the PLL2 base clock.
-+	 */
-+	of_property_read_string_index(node, "clock-output-names",
-+				      SUN4I_A10_PLL2_2X, &clk_name);
-+	clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
-+							    parent,
-+							    CLK_SET_RATE_PARENT,
-+							    1, 2);
-+	WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
-+
-+	/* PLL2-4x */
-+	of_property_read_string_index(node, "clock-output-names",
-+				      SUN4I_A10_PLL2_4X, &clk_name);
-+	clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
-+							    parent,
-+							    CLK_SET_RATE_PARENT,
-+							    1, 1);
-+	WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
-+
-+	/* PLL2-8x */
-+	of_property_read_string_index(node, "clock-output-names",
-+				      SUN4I_A10_PLL2_8X, &clk_name);
-+	clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
-+							    parent,
-+							    CLK_SET_RATE_PARENT,
-+							    2, 1);
-+	WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
-+
-+	clk_data->clks = clks;
-+	clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
-+	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	return;
-+
-+err_free_multiplier:
-+	kfree(mult);
-+err_free_gate:
-+	kfree(gate);
-+err_unregister_prediv:
-+	clk_unregister_divider(prediv_clk);
-+err_free_array:
-+	kfree(clks);
-+err_free_data:
-+	kfree(clk_data);
-+err_unmap:
-+	iounmap(reg);
-+}
-+CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup);
-diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h
-new file mode 100644
-index 0000000..071c811
---- /dev/null
-+++ b/include/dt-bindings/clock/sun4i-a10-pll2.h
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2015 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This file is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
-+#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
-+
-+#define SUN4I_A10_PLL2_1X	0
-+#define SUN4I_A10_PLL2_2X	1
-+#define SUN4I_A10_PLL2_4X	2
-+#define SUN4I_A10_PLL2_8X	3
-+
-+#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
--- 
-cgit v0.12
-
diff --git a/libre/linux-libre-lts/0006-clk-sunxi-pll2-Add-A13-support.patch b/libre/linux-libre-lts/0006-clk-sunxi-pll2-Add-A13-support.patch
deleted file mode 100644
index e8c807c25..000000000
--- a/libre/linux-libre-lts/0006-clk-sunxi-pll2-Add-A13-support.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From eb662f854710e6a438789a4b0d1d0cce8c12379d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 21 Sep 2015 13:32:43 +0200
-Subject: [PATCH 6/9] clk: sunxi: pll2: Add A13 support
-
-The A13, unlike the A10 and A20, doesn't use a pass-through exception for
-the 0 value in the pre and post dividers, but increments all the values
-written in the register by one.
-
-Add an exception for both these cases to handle them nicely.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Reviewed-by: Chen-Yu Tsai <wens@csie.org>
----
- drivers/clk/sunxi/clk-a10-pll2.c | 38 +++++++++++++++++++++++++++++++++-----
- 1 file changed, 33 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
-index a57742a..5484c31 100644
---- a/drivers/clk/sunxi/clk-a10-pll2.c
-+++ b/drivers/clk/sunxi/clk-a10-pll2.c
-@@ -41,9 +41,15 @@
- 
- #define SUN4I_PLL2_OUTPUTS		4
- 
-+struct sun4i_pll2_data {
-+	u32	post_div_offset;
-+	u32	pre_div_flags;
-+};
-+
- static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
- 
--static void __init sun4i_pll2_setup(struct device_node *node)
-+static void __init sun4i_pll2_setup(struct device_node *node,
-+				    struct sun4i_pll2_data *data)
- {
- 	const char *clk_name = node->name, *parent;
- 	struct clk **clks, *base_clk, *prediv_clk;
-@@ -70,8 +76,7 @@ static void __init sun4i_pll2_setup(struct device_node *node)
- 					  parent, 0, reg,
- 					  SUN4I_PLL2_PRE_DIV_SHIFT,
- 					  SUN4I_PLL2_PRE_DIV_WIDTH,
--					  CLK_DIVIDER_ONE_BASED |
--					  CLK_DIVIDER_ALLOW_ZERO,
-+					  data->pre_div_flags,
- 					  &sun4i_a10_pll2_lock);
- 	if (!prediv_clk) {
- 		pr_err("Couldn't register the prediv clock\n");
-@@ -122,7 +127,7 @@ static void __init sun4i_pll2_setup(struct device_node *node)
- 	 */
- 	val = readl(reg);
- 	val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
--	val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT;
-+	val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
- 	writel(val, reg);
- 
- 	of_property_read_string_index(node, "clock-output-names",
-@@ -185,4 +190,27 @@ err_free_data:
- err_unmap:
- 	iounmap(reg);
- }
--CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup);
-+
-+static struct sun4i_pll2_data sun4i_a10_pll2_data = {
-+	.pre_div_flags	= CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
-+};
-+
-+static void __init sun4i_a10_pll2_setup(struct device_node *node)
-+{
-+	sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
-+}
-+
-+CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
-+	       sun4i_a10_pll2_setup);
-+
-+static struct sun4i_pll2_data sun5i_a13_pll2_data = {
-+	.post_div_offset	= 1,
-+};
-+
-+static void __init sun5i_a13_pll2_setup(struct device_node *node)
-+{
-+	sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
-+}
-+
-+CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
-+	       sun5i_a13_pll2_setup);
--- 
-cgit v0.12
-
diff --git a/libre/linux-libre-lts/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch b/libre/linux-libre-lts/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch
deleted file mode 100644
index 9704d17d6..000000000
--- a/libre/linux-libre-lts/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From 59f0ec231f397001801264063db3b6dcc3eef590 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 1 Dec 2015 12:14:52 +0100
-Subject: [PATCH 9/9] clk: sunxi: pll2: Fix clock running too fast
-
-Contrary to what the datasheet says, the pre divider doesn't seem to be
-incremented by one in the PLL2, but just uses the value from the register,
-with 0 being a bypass.
-
-This fixes the audio playing too fast.
-
-Since we now have the same pre-divider flags, and the only difference with
-the A10 is the post-divider offset, also remove the structure to just pass
-the offset as an argument.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support")
-Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
----
- drivers/clk/sunxi/clk-a10-pll2.c | 23 +++++------------------
- 1 file changed, 5 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
-index 5484c31..0ee1f36 100644
---- a/drivers/clk/sunxi/clk-a10-pll2.c
-+++ b/drivers/clk/sunxi/clk-a10-pll2.c
-@@ -41,15 +41,10 @@
- 
- #define SUN4I_PLL2_OUTPUTS		4
- 
--struct sun4i_pll2_data {
--	u32	post_div_offset;
--	u32	pre_div_flags;
--};
--
- static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
- 
- static void __init sun4i_pll2_setup(struct device_node *node,
--				    struct sun4i_pll2_data *data)
-+				    int post_div_offset)
- {
- 	const char *clk_name = node->name, *parent;
- 	struct clk **clks, *base_clk, *prediv_clk;
-@@ -76,7 +71,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
- 					  parent, 0, reg,
- 					  SUN4I_PLL2_PRE_DIV_SHIFT,
- 					  SUN4I_PLL2_PRE_DIV_WIDTH,
--					  data->pre_div_flags,
-+					  CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
- 					  &sun4i_a10_pll2_lock);
- 	if (!prediv_clk) {
- 		pr_err("Couldn't register the prediv clock\n");
-@@ -127,7 +122,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
- 	 */
- 	val = readl(reg);
- 	val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
--	val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
-+	val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
- 	writel(val, reg);
- 
- 	of_property_read_string_index(node, "clock-output-names",
-@@ -191,25 +186,17 @@ err_unmap:
- 	iounmap(reg);
- }
- 
--static struct sun4i_pll2_data sun4i_a10_pll2_data = {
--	.pre_div_flags	= CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
--};
--
- static void __init sun4i_a10_pll2_setup(struct device_node *node)
- {
--	sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
-+	sun4i_pll2_setup(node, 0);
- }
- 
- CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
- 	       sun4i_a10_pll2_setup);
- 
--static struct sun4i_pll2_data sun5i_a13_pll2_data = {
--	.post_div_offset	= 1,
--};
--
- static void __init sun5i_a13_pll2_setup(struct device_node *node)
- {
--	sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
-+	sun4i_pll2_setup(node, 1);
- }
- 
- CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
--- 
-cgit v0.12
-
diff --git a/libre/linux-libre-lts/PKGBUILD b/libre/linux-libre-lts/PKGBUILD
index 2d4e8b5d9..97c735508 100644
--- a/libre/linux-libre-lts/PKGBUILD
+++ b/libre/linux-libre-lts/PKGBUILD
@@ -52,13 +52,9 @@ source=("http://linux-libre.fsfla.org/pub/linux-libre/releases/${_pkgbasever}/li
         "https://repo.parabola.nu/other/rcn-libre/patches/${_pkgver%-*}/rcn-libre-${_pkgver%-*}-${rcnrel}.patch.sig"
         '0001-ARM-sunxi-Add-R8-support.patch'
         '0002-ARM-sun5i-Add-CHIP-DTS.patch'
-        '0003-ARM-sun5i-chip-Enable-the-audio-codec.patch'
-        '0004-ARM-sun5i-Add-R8-DTSI.patch'
-        '0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch'
-        '0006-clk-sunxi-pll2-Add-A13-support.patch'
-        '0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch'
-        '0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch'
-        '0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch'
+        '0003-ARM-sun5i-Add-R8-DTSI.patch'
+        '0004-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch'
+        '0005-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch'
         '0001-ARM-atags-add-support-for-Marvell-s-u-boot.patch'
         '0002-ARM-atags-fdt-retrieve-MAC-addresses-from-Marvell-bo.patch'
         '0003-SMILE-Plug-device-tree-file.patch'
@@ -87,15 +83,11 @@ sha256sums=('48b2e5ea077d0a0bdcb205e67178e8eb5b2867db3b2364b701dbc801d9755324'
             '0a6f76bbc03ae6e846a4ba4e31bbc0a40b1ae538c1271defcbe3089e00a4b53d'
             '3743d0478507d160f24326241831df8c4d3f2e268bcaf2f62dfe2ef5e8a69188'
             'SKIP'
-            '5a5d13a8e778742d6971a06d2f4d69fa5994cf3089f0344f12a24ad9cedd2d8a'
-            'b16eae7c4f2ea4733577c62a745e63c8e0a2d26fe5f7edb8e64cf37bdc3e5a0a'
-            'e2b2f19a971e2a7fd2762cc812184c02c84b684ce503bc7b227222a0e70f7ea4'
-            '2697bfb457abd158c0e33b17a0c8811f4afed1937318f8b28db879295299e79a'
-            '83ba4022c82713ce91227f68a25c1e49ff00d3bfc98d9beb68539568418e626c'
-            'aaad781c9d282f58f8222dd62a783fd3da5584598c281ec5e0287a0811f5165e'
-            '07b345e43e88d1725f3a677ed667796d47d6d87709493ae68caa39079a0a9324'
-            'faaa061dab16abf0748139ce6ce226c263d97e81607065e7046edd2c7d21c837'
-            '1d9281271b2335b1c2874f2ed0dcd627dc1fd9f5360e3f39d6c91d5e01435128'
+            '349691937f0a2881c5fc981d7fb85f64ad3c341ce77a716638d328750d3e9f41'
+            '26274259a896a6a362bf89a5ba014c01c5126c646dcd50b51255d94743a9ad7f'
+            '80d426c53296b0a04d7817caafe628135ac28abfe32cc7f4740049b89d7bd956'
+            '32673476cec6024851c5e084f920c72a4c5297c092d0b40a65ab5c05089bb36e'
+            'fdb50c0b420d374de0552412a5b65f568eda3bf9dc896682578a74797c5c4dab'
             '203b07cc241f2374d1e18583fc9940cc69da134f992bff65a8b376c717aa7ea7'
             '28fb8c937c2a0dc824ea755efba26ac5a4555f9a97d79f4e31f24b23c5eae59c'
             '39bfd7f6e2df0b87b52488462edb2fbcfaf9e3eb2a974fc7b3bc22147352fece'
@@ -133,15 +125,12 @@ prepare() {
     git apply -v "${srcdir}/rcn-libre-${_pkgver%-*}-${rcnrel}.patch"
 
     # Parabola patches
+    # add C.H.I.P single-board computer support
     patch -p1 -i "${srcdir}/0001-ARM-sunxi-Add-R8-support.patch"
     patch -p1 -i "${srcdir}/0002-ARM-sun5i-Add-CHIP-DTS.patch"
-    patch -p1 -i "${srcdir}/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch"
-    patch -p1 -i "${srcdir}/0004-ARM-sun5i-Add-R8-DTSI.patch"
-    patch -p1 -i "${srcdir}/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch"
-    patch -p1 -i "${srcdir}/0006-clk-sunxi-pll2-Add-A13-support.patch"
-    patch -p1 -i "${srcdir}/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch"
-    patch -p1 -i "${srcdir}/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch"
-    patch -p1 -i "${srcdir}/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch"
+    patch -p1 -i "${srcdir}/0003-ARM-sun5i-Add-R8-DTSI.patch"
+    patch -p1 -i "${srcdir}/0004-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch"
+    patch -p1 -i "${srcdir}/0005-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch"
 
     # ALARM patches
     patch -p1 -i "${srcdir}/0001-ARM-atags-add-support-for-Marvell-s-u-boot.patch"