From 14e4651135a22e5c704d1d61b537478fc1e69f74 Mon Sep 17 00:00:00 2001 From: David P Date: Tue, 4 Jan 2022 16:50:44 -0500 Subject: updpkg: libre/linux-libre 5.15.12-1 Signed-off-by: David P --- ...el_pstate-ITMT-support-for-overclocked-sy.patch | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 libre/linux-libre/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch (limited to 'libre/linux-libre/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch') diff --git a/libre/linux-libre/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch b/libre/linux-libre/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch new file mode 100644 index 000000000..910c03b59 --- /dev/null +++ b/libre/linux-libre/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch @@ -0,0 +1,55 @@ +From a6e9d2e9ec1a81ff2b45a986bc320f28dc155f1d Mon Sep 17 00:00:00 2001 +From: Srinivas Pandruvada +Date: Thu, 18 Nov 2021 21:18:01 -0800 +Subject: [PATCH 4/6] cpufreq: intel_pstate: ITMT support for overclocked + system + +On systems with overclocking enabled, CPPC Highest Performance can be +hard coded to 0xff. In this case even if we have cores with different +highest performance, ITMT can't be enabled as the current implementation +depends on CPPC Highest Performance. + +On such systems we can use MSR_HWP_CAPABILITIES maximum performance field +when CPPC.Highest Performance is 0xff. + +Due to legacy reasons, we can't solely depend on MSR_HWP_CAPABILITIES as +in some older systems CPPC Highest Performance is the only way to identify +different performing cores. + +Reported-by: Michael Larabel +Signed-off-by: Srinivas Pandruvada +--- + drivers/cpufreq/intel_pstate.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c +index e15c3bc17a55..8a2c6b58b652 100644 +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -335,6 +335,8 @@ static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) + + static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); + ++#define CPPC_MAX_PERF U8_MAX ++ + static void intel_pstate_set_itmt_prio(int cpu) + { + struct cppc_perf_caps cppc_perf; +@@ -345,6 +347,14 @@ static void intel_pstate_set_itmt_prio(int cpu) + if (ret) + return; + ++ /* ++ * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. ++ * In this case we can't use CPPC.highest_perf to enable ITMT. ++ * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. ++ */ ++ if (cppc_perf.highest_perf == CPPC_MAX_PERF) ++ cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); ++ + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to +-- +2.34.1 + -- cgit v1.2.3