diff options
Diffstat (limited to 'libre/linux-libre-pae/0013-pinctrl-sunrisepoint-Add-missing-Interrupt-Status-re.patch')
-rw-r--r-- | libre/linux-libre-pae/0013-pinctrl-sunrisepoint-Add-missing-Interrupt-Status-re.patch | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/libre/linux-libre-pae/0013-pinctrl-sunrisepoint-Add-missing-Interrupt-Status-re.patch b/libre/linux-libre-pae/0013-pinctrl-sunrisepoint-Add-missing-Interrupt-Status-re.patch new file mode 100644 index 000000000..ca540525b --- /dev/null +++ b/libre/linux-libre-pae/0013-pinctrl-sunrisepoint-Add-missing-Interrupt-Status-re.patch @@ -0,0 +1,35 @@ +From adb810e1819b859aec1f8eb4c5611bc6ebe82137 Mon Sep 17 00:00:00 2001 +From: Boyan Ding <boyan.j.ding@gmail.com> +Date: Wed, 1 Jan 2020 11:44:49 -0800 +Subject: [PATCH 13/13] pinctrl: sunrisepoint: Add missing Interrupt Status + register offset + +Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status +offset") removes default interrupt status offset of GPIO controllers, +with previous commits explicitly providing the previously default +offsets. However, the is_offset value in SPTH_COMMUNITY is missing, +preventing related irq from being properly detected and handled. + +Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset") +Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745 +Cc: stable@vger.kernel.org +Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> +--- + drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +index 44d7f50bbc82..d936e7aa74c4 100644 +--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c ++++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +@@ -49,6 +49,7 @@ + .padown_offset = SPT_PAD_OWN, \ + .padcfglock_offset = SPT_PADCFGLOCK, \ + .hostown_offset = SPT_HOSTSW_OWN, \ ++ .is_offset = SPT_GPI_IS, \ + .ie_offset = SPT_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ +-- +2.24.1 + |