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author | Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> | 2020-05-24 04:19:21 +0200 |
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committer | Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> | 2020-05-24 04:24:43 +0200 |
commit | e9d3becf4bc982a613f25e0ede0dc4a4c7864c07 (patch) | |
tree | a2fed3d7c9b0bae4534a81faaf49b231ddf1b5fc /kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch | |
parent | 4c932f5681f154e2b9cd329a9b982d76642318fb (diff) | |
download | abslibre-e9d3becf4bc982a613f25e0ede0dc4a4c7864c07.tar.gz abslibre-e9d3becf4bc982a613f25e0ede0dc4a4c7864c07.tar.bz2 abslibre-e9d3becf4bc982a613f25e0ede0dc4a4c7864c07.zip |
kernels: remove linux-libre-x86_64
This kernel has been replaced by linux-libre-64 in libre in an
attempt to unify all 64bit kernels made for 32bit rootfs.
This has been tested on a Lenovo Thinkpad X200 running a fully
free version of Coreboot 4.9 (no microcode or other nonfree
binaries).
The only regresion that I noticed is that beside having the
following line in /etc/mkinitcpio.conf:
MODULES=(i915 netconsole)
The i915 driver seem to be loaded late in the boot process
as I can only see notice a resolution change about when the
rootfs is mounted and that init is started.
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Diffstat (limited to 'kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch')
-rw-r--r-- | kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch b/kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch deleted file mode 100644 index 952bb8d55..000000000 --- a/kernels/linux-libre-x86_64/0010-drm-i915-Fix-audio-power-up-sequence-for-gen10-displ.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 3a8fe5edd1f716667d7f1ebd4f06bc808bf89a6d Mon Sep 17 00:00:00 2001 -From: Kai Vehmanen <kai.vehmanen@linux.intel.com> -Date: Thu, 3 Oct 2019 11:55:30 +0300 -Subject: [PATCH 10/13] drm/i915: Fix audio power up sequence for gen10+ - display - -On platfroms with gen10+ display, driver must set the enable bit of -AUDIO_PIN_BUF_CTL register before transactions with the HDA controller -can proceed. Add setting this bit to the audio power up sequence. - -Failing to do this resulted in errors during display audio codec probe, -and failures during resume from suspend. - -Note: We may also need to disable the bit afterwards, but there are -still unresolved issues with that. - -Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214 -Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> -Signed-off-by: Jani Nikula <jani.nikula@intel.com> -Link: https://patchwork.freedesktop.org/patch/msgid/20191003085531.30990-1-kai.vehmanen@linux.intel.com ---- - drivers/gpu/drm/i915/display/intel_audio.c | 5 +++++ - drivers/gpu/drm/i915/i915_reg.h | 2 ++ - 2 files changed, 7 insertions(+) - -diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c -index 439bc0a93410..440b33762fef 100644 ---- a/drivers/gpu/drm/i915/display/intel_audio.c -+++ b/drivers/gpu/drm/i915/display/intel_audio.c -@@ -860,6 +860,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) - /* Force CDCLK to 2*BCLK as long as we need audio powered. */ - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) - glk_force_audio_cdclk(dev_priv, true); -+ -+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) -+ I915_WRITE(AUD_PIN_BUF_CTL, -+ (I915_READ(AUD_PIN_BUF_CTL) | -+ AUD_PIN_BUF_ENABLE)); - } - - return ret; -diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h -index e1fe356463ec..ccfea9c2b8bf 100644 ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -9105,6 +9105,8 @@ enum { - #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) - - #define AUD_FREQ_CNTRL _MMIO(0x65900) -+#define AUD_PIN_BUF_CTL _MMIO(0x48414) -+#define AUD_PIN_BUF_ENABLE REG_BIT(31) - - /* - * HSW - ICL power wells --- -2.24.1 - |