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| author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-09-21 06:46:11 -0300 |
|---|---|---|
| committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-09-21 06:46:11 -0300 |
| commit | 68cebe4b6a7b7266c5ea9d6085a3c15aaf44496a (patch) | |
| tree | 7676bc1736ac0be28384f4fda39ad9468ab8fb7a /cross/cross-gcc/gcc-xtensa.patch | |
| parent | 536f888e99b11c27a64abdc3404f15da8cc0befa (diff) | |
| download | abslibre-68cebe4b6a7b7266c5ea9d6085a3c15aaf44496a.tar.gz abslibre-68cebe4b6a7b7266c5ea9d6085a3c15aaf44496a.tar.bz2 abslibre-68cebe4b6a7b7266c5ea9d6085a3c15aaf44496a.zip | |
cross-gcc: update xtensa patch
Diffstat (limited to 'cross/cross-gcc/gcc-xtensa.patch')
| -rw-r--r-- | cross/cross-gcc/gcc-xtensa.patch | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/cross/cross-gcc/gcc-xtensa.patch b/cross/cross-gcc/gcc-xtensa.patch new file mode 100644 index 000000000..b26cc568a --- /dev/null +++ b/cross/cross-gcc/gcc-xtensa.patch @@ -0,0 +1,92 @@ +diff --git a/include/xtensa-config.h b/include/xtensa-config.h +index 5ae4c80..8397564 100644 +--- a/include/xtensa-config.h ++++ b/include/xtensa-config.h +@@ -43,10 +43,7 @@ + #define XCHAL_HAVE_L32R 1 + + #undef XSHAL_USE_ABSOLUTE_LITERALS +-#define XSHAL_USE_ABSOLUTE_LITERALS 0 +- +-#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ ++#define XSHAL_USE_ABSOLUTE_LITERALS 1 + + #undef XCHAL_HAVE_MAC16 + #define XCHAL_HAVE_MAC16 0 +@@ -58,10 +55,10 @@ + #define XCHAL_HAVE_MUL32 1 + + #undef XCHAL_HAVE_MUL32_HIGH +-#define XCHAL_HAVE_MUL32_HIGH 0 ++#define XCHAL_HAVE_MUL32_HIGH 1 + + #undef XCHAL_HAVE_DIV32 +-#define XCHAL_HAVE_DIV32 1 ++#define XCHAL_HAVE_DIV32 0 + + #undef XCHAL_HAVE_NSA + #define XCHAL_HAVE_NSA 1 +@@ -102,8 +99,6 @@ + #undef XCHAL_HAVE_FP_RSQRT + #define XCHAL_HAVE_FP_RSQRT 0 + +-#undef XCHAL_HAVE_DFP_accel +-#define XCHAL_HAVE_DFP_accel 0 + #undef XCHAL_HAVE_WINDOWED + #define XCHAL_HAVE_WINDOWED 1 + +@@ -118,32 +113,32 @@ + + + #undef XCHAL_ICACHE_SIZE +-#define XCHAL_ICACHE_SIZE 16384 ++#define XCHAL_ICACHE_SIZE 0 + + #undef XCHAL_DCACHE_SIZE +-#define XCHAL_DCACHE_SIZE 16384 ++#define XCHAL_DCACHE_SIZE 0 + + #undef XCHAL_ICACHE_LINESIZE +-#define XCHAL_ICACHE_LINESIZE 32 ++#define XCHAL_ICACHE_LINESIZE 16 + + #undef XCHAL_DCACHE_LINESIZE +-#define XCHAL_DCACHE_LINESIZE 32 ++#define XCHAL_DCACHE_LINESIZE 16 + + #undef XCHAL_ICACHE_LINEWIDTH +-#define XCHAL_ICACHE_LINEWIDTH 5 ++#define XCHAL_ICACHE_LINEWIDTH 4 + + #undef XCHAL_DCACHE_LINEWIDTH +-#define XCHAL_DCACHE_LINEWIDTH 5 ++#define XCHAL_DCACHE_LINEWIDTH 4 + + #undef XCHAL_DCACHE_IS_WRITEBACK +-#define XCHAL_DCACHE_IS_WRITEBACK 1 ++#define XCHAL_DCACHE_IS_WRITEBACK 0 + + + #undef XCHAL_HAVE_MMU + #define XCHAL_HAVE_MMU 1 + + #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 ++#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 + + + #undef XCHAL_HAVE_DEBUG +@@ -156,8 +151,11 @@ + #define XCHAL_NUM_DBREAK 2 + + #undef XCHAL_DEBUGLEVEL +-#define XCHAL_DEBUGLEVEL 6 ++#define XCHAL_DEBUGLEVEL 4 ++ + ++#undef XCHAL_EXCM_LEVEL ++#define XCHAL_EXCM_LEVEL 3 + + #undef XCHAL_MAX_INSTRUCTION_SIZE + #define XCHAL_MAX_INSTRUCTION_SIZE 3 |